1. Field
Example embodiments relate to electrostatic discharge (ESD) protection, and more particularly, to a transistor with electrical overstress (EOS) protection, a clamp device including the transistor and an ESD protection circuit including the clamp device.
2. Description of the Related Art
Electrostatic discharge (ESD) is a phenomenon where a finite quantity of electrostatic charge may be rapidly transferred between bodies or surfaces at different electrostatic potentials. The duration of ESD events may range from picoseconds to microseconds. Electrical overstress (EOS) may be an electrical shock that occurs when a product is exposed to a leakage current or voltage usually from a power supply device or test equipment. The duration of EOS events may range from nanoseconds to milliseconds. As described above, ESD and EOS are different with regards to the duration of electrical transient pulse widths.
A thin insulating layer, e.g., a gate oxide layer, may be damaged, when an ESD event or EOS event occurs in a device manufactured by a complementary metal-oxide semiconductor (CMOS) process. Therefore, a protection circuit for ESD and EOS may be required. As a semiconductor technology advances, the degree of integration of semiconductor devices may increase and power consumption of semiconductor devices may decrease, and thus, the semiconductor devices may be more easily exposed to ESD. When the thickness of a gate oxide layer of a MOS transistor ranges from about 3 nm to about 4 nm, an insulating layer may be destroyed by a voltage ranging from about 3 V to about 4 V, and thus, there may be an increasing demand for a protection circuit protecting an internal core from an ESD event and EOS event. For meeting the demand, many protection technologies have been developed for protecting the internal core from an ESD event and EOS event.
FIG. 1 is a circuit diagram illustrating a conventional gate-grounded n-channel metal oxide semiconductor (GGNMOS) transistor. FIG. 2 is a circuit diagram illustrating a conventional gate-coupled NMOS (GCNMOS) transistor. The GGNMOS transistor of FIG. 1 has a configuration where a gate, a source, and a body may all be grounded, and uses a snap-back phenomenon. The GGNMOS transistor may be capable of protecting the internal core from an EOS event that has a relatively long duration of electrical transient pulse widths. However, the GGNMOS transistor may not be efficiently capable of protecting the internal core from an ESD event because an ESD current may flow into the internal core until triggering a voltage level of the transistor. The ESD current may be discharged through the transistor instead of flowing into the internal core at the triggering voltage level of the transistor.
A GCNMOS transistor having a configuration where a silicide blocking layer (SBL) is eliminated may be employed. The configuration of the GCNMOS may be capable of protecting the internal core from an ESD event that has a relatively short duration of electrical transient pulse widths. However, the GCNMOS may not be capable of protecting the internal core from an EOS event that has a relatively long duration of electrical transient pulse widths. When the GCNMOS of FIG. 2 is implemented with a bipolar insulated-gate field-effect transistor (BIGFET) manufactured in a relatively large size, and the EOS is applied to the BIGFET, a gate of the BIGFET may be in an off state and the BIGFET may be damaged due to a parasitic bipolar operation. Generally, a center portion of the BIGFET may be easily damaged. An on-time of the gate may be increased so as to prevent or reduce the damage. For example, a capacitance of a capacitor C or a resistance of a resistor R may be increased in FIG. 2. However, an additional space may be required so as to increase the capacitance C of the capacitor or the resistance of the resistor R.